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<p>MIPI CSI Tx Subsystem configuration structure.  
 <a href="struct_x_csi2_tx_ss___config.html#details">More...</a></p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:aa81e5cafcc000adaca1699fa0a585fe9"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#aa81e5cafcc000adaca1699fa0a585fe9">DeviceId</a></td></tr>
<tr class="memdesc:aa81e5cafcc000adaca1699fa0a585fe9"><td class="mdescLeft">&#160;</td><td class="mdescRight">DeviceId is the unique ID of the device.  <a href="#aa81e5cafcc000adaca1699fa0a585fe9">More...</a><br/></td></tr>
<tr class="separator:aa81e5cafcc000adaca1699fa0a585fe9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a81d81ca026f814b36aaa4f640886fb9b"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#a81d81ca026f814b36aaa4f640886fb9b">BaseAddr</a></td></tr>
<tr class="memdesc:a81d81ca026f814b36aaa4f640886fb9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">BaseAddress is the physical base address of the subsystem address range.  <a href="#a81d81ca026f814b36aaa4f640886fb9b">More...</a><br/></td></tr>
<tr class="separator:a81d81ca026f814b36aaa4f640886fb9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e3d185b3246a66d9fa0c87be4d76170"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#a7e3d185b3246a66d9fa0c87be4d76170">HighAddr</a></td></tr>
<tr class="memdesc:a7e3d185b3246a66d9fa0c87be4d76170"><td class="mdescLeft">&#160;</td><td class="mdescRight">HighAddress is the physical MAX address of the subsystem address range.  <a href="#a7e3d185b3246a66d9fa0c87be4d76170">More...</a><br/></td></tr>
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<tr class="memitem:a39ee5c2c2b06e24f427cf41d4fc9de81"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#a39ee5c2c2b06e24f427cf41d4fc9de81">LanesPresent</a></td></tr>
<tr class="memdesc:a39ee5c2c2b06e24f427cf41d4fc9de81"><td class="mdescLeft">&#160;</td><td class="mdescRight">Active Lanes programming optimization enabled.  <a href="#a39ee5c2c2b06e24f427cf41d4fc9de81">More...</a><br/></td></tr>
<tr class="separator:a39ee5c2c2b06e24f427cf41d4fc9de81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa783a6306cb5026589bc4ea1b100367d"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#aa783a6306cb5026589bc4ea1b100367d">PixelFormat</a></td></tr>
<tr class="memdesc:aa783a6306cb5026589bc4ea1b100367d"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> 1 - Single pixel per beat
</pre><p> 2 - Dual pixels per beat 4 - Quad pixels per beat  <a href="#aa783a6306cb5026589bc4ea1b100367d">More...</a><br/></td></tr>
<tr class="separator:aa783a6306cb5026589bc4ea1b100367d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a941dcb9a60baa61a24bcb28260689183"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#a941dcb9a60baa61a24bcb28260689183">CsiBuffDepth</a></td></tr>
<tr class="memdesc:a941dcb9a60baa61a24bcb28260689183"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line buffer Depth set.  <a href="#a941dcb9a60baa61a24bcb28260689183">More...</a><br/></td></tr>
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<tr class="memitem:a8df2677fd796d73da2e0c226ef1d1ef8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#a8df2677fd796d73da2e0c226ef1d1ef8">DphyLineRate</a></td></tr>
<tr class="memdesc:a8df2677fd796d73da2e0c226ef1d1ef8"><td class="mdescLeft">&#160;</td><td class="mdescRight">DPHY Line Rate ranging from 80-1500 Mbps.  <a href="#a8df2677fd796d73da2e0c226ef1d1ef8">More...</a><br/></td></tr>
<tr class="separator:a8df2677fd796d73da2e0c226ef1d1ef8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8364cfcd48d9087a1657c96241dad16e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#a8364cfcd48d9087a1657c96241dad16e">IsDphyRegIntfcPresent</a></td></tr>
<tr class="memdesc:a8364cfcd48d9087a1657c96241dad16e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for DPHY register interface presence.  <a href="#a8364cfcd48d9087a1657c96241dad16e">More...</a><br/></td></tr>
<tr class="separator:a8364cfcd48d9087a1657c96241dad16e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad372aabbf5a19e00a4add55dcf18c455"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#ad372aabbf5a19e00a4add55dcf18c455">FEGenEnabled</a></td></tr>
<tr class="memdesc:ad372aabbf5a19e00a4add55dcf18c455"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame End Generation enabled flag.  <a href="#ad372aabbf5a19e00a4add55dcf18c455">More...</a><br/></td></tr>
<tr class="separator:ad372aabbf5a19e00a4add55dcf18c455"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac1f1614d0982366c88534f12b5676b52"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_sub_core_csi2_tx.html">SubCoreCsi2Tx</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#ac1f1614d0982366c88534f12b5676b52">CsiInfo</a></td></tr>
<tr class="memdesc:ac1f1614d0982366c88534f12b5676b52"><td class="mdescLeft">&#160;</td><td class="mdescRight">CSI sub-core configuration.  <a href="#ac1f1614d0982366c88534f12b5676b52">More...</a><br/></td></tr>
<tr class="separator:ac1f1614d0982366c88534f12b5676b52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d7815d15cd570324a809f44db56f550"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_sub_core_csi2_tx.html">SubCoreCsi2Tx</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx_ss___config.html#a5d7815d15cd570324a809f44db56f550">DphyInfo</a></td></tr>
<tr class="memdesc:a5d7815d15cd570324a809f44db56f550"><td class="mdescLeft">&#160;</td><td class="mdescRight">DPHY sub-core configuration.  <a href="#a5d7815d15cd570324a809f44db56f550">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>MIPI CSI Tx Subsystem configuration structure. </p>
<p>Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem </p>
</div><h2 class="groupheader">Field Documentation</h2>
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<p>BaseAddress is the physical base address of the subsystem address range. </p>

<p>Referenced by <a class="el" href="group__csi2txss.html#ga4f003f0f154d0a6f6d7c06498ff3c655">Csi2TxSs_IntrExample()</a>, <a class="el" href="group__csi2txss.html#ga1e0a474f9469d041cee3f863c5a6de97">Csi2TxSs_SelfTestExample()</a>, and <a class="el" href="group__csi2txss.html#ga05a335318d3ee341c8288279cf4d8683">XCsi2TxSs_CfgInitialize()</a>.</p>

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          <td class="memname">u32 XCsi2TxSs_Config::CsiBuffDepth</td>
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<p>Line buffer Depth set. </p>

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          <td class="memname"><a class="el" href="struct_sub_core_csi2_tx.html">SubCoreCsi2Tx</a> XCsi2TxSs_Config::CsiInfo</td>
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<p>CSI sub-core configuration. </p>

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<p>DeviceId is the unique ID of the device. </p>

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          <td class="memname"><a class="el" href="struct_sub_core_csi2_tx.html">SubCoreCsi2Tx</a> XCsi2TxSs_Config::DphyInfo</td>
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<p>DPHY sub-core configuration. </p>

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          <td class="memname">u32 XCsi2TxSs_Config::DphyLineRate</td>
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<p>DPHY Line Rate ranging from 80-1500 Mbps. </p>

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          <td class="memname">u32 XCsi2TxSs_Config::FEGenEnabled</td>
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<p>Frame End Generation enabled flag. </p>

<p>Referenced by <a class="el" href="group__csi2txss.html#ga20a5a3fc9695ca1ac7fdbea4300da836">XCsi2TxSs_Configure()</a>, <a class="el" href="group__csi2txss.html#ga655b4f5658f8e8dc4ebc550fc4c6e8f0">XCsi2TxSs_GetLineCountForVC()</a>, <a class="el" href="group__csi2txss.html#ga05e607ece4b52c59fa349f5f2e42976f">XCsi2TxSs_IntrDisable()</a>, and <a class="el" href="group__csi2txss.html#ga66c4f55bd50f54c8712fd8b2c2d70c0b">XCsi2TxSs_SetLineCountForVC()</a>.</p>

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<p>HighAddress is the physical MAX address of the subsystem address range. </p>

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<p>Flag for DPHY register interface presence. </p>

<p>Referenced by <a class="el" href="group__csi2txss.html#gac74b7b2f7be7e695c3034f45d681c8ed">XCsi2TxSs_Activate()</a>, <a class="el" href="group__csi2txss.html#ga05a335318d3ee341c8288279cf4d8683">XCsi2TxSs_CfgInitialize()</a>, and <a class="el" href="group__csi2txss.html#gad5067597d1a3f39b5be158ce026e3f8c">XCsi2TxSs_ReportCoreInfo()</a>.</p>

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<p>Active Lanes programming optimization enabled. </p>

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<p><pre class="fragment"> 1 - Single pixel per beat
</pre><p> 2 - Dual pixels per beat 4 - Quad pixels per beat </p>

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